Method of maximizing chip yield for semiconductor wafers

ABSTRACT

A method of fabricating semiconductor chips includes the steps of optimizing a number of chips that geometrically fit on a wafer and maximizing chip yield for the wafer by considering chips located in a normally rejectable location and utilizing yield probability data for the chip in the normally rejectable locations to weight the probability of an acceptable chip such that if the probability is above a threshold value the chips are not rejected. This results in an increased chip yield for semiconductor wafers.

BACKGROUND

1. Technical Field

This disclosure relates to semiconductor wafers and more particularly,to a method of maximizing the overall yield of chips per wafer.

2. Description of the Related Art

Semiconductor crystal wafers, such as those made of silicon, are used asa substrate for processing integrated circuit chips. As processing hasimproved over the years wafer diameters have increased to their currentsize of approximately 8 inches and greater. Wafers are generally slicedoff from a large silicon crystal ingot and are therefore generallycircular in shape.

Decreasing feature size for integrated circuit chips has increased thecriticality of the planarity of the wafer. Today, with 0.35 micronfeatures becoming widespread, surface planarity is assuming newimportance, since it offers the key to boosting performance.

Chemical mechanical polishing (CMP) is a process for improving thesurface planarity of a semiconductor wafer and involves the use ofmechanical pad polishing systems usually with a silica-based slurry. CMPoffers a practical approach to achieving the important advantage ofglobal wafer planarity. However, CMP systems for global planarizationhave certain limitations. These limitations include low waferthroughput, polished surface non-uniformity and a problem related topolishing uniformity known as "edge exclusion". Edge exclusion occurswhen too much of the semiconductor wafer is polished. This causes theedge or outer portion of the wafer to be unusable for integrated circuitfabrication. Wafer polish throughput and polish uniformity are importantprocess parameters, because they also directly affect the number ofintegrated circuit chips that a fabrication facility can produce for agiven period of time.

As mentioned above wafers are circular in shape. Integrated circuitchips are rectangular or square in shape. Since the integrated circuitchips are formed on the wafer, there are areas of the wafer that cannotbe used based on the geometry mismatch alone. The area of unused spaceis further increased due to increased edge exclusion on the wafer. Inaddition to polishing, edge exclusions can be created by wafer handlingdevices. An edge exclusion can be defined on a given wafer by handlingmarks on that wafer. For example, a handling mark that extends furtherinward from the edge of the wafer than the polishing edge, defines theedge exclusion for that wafer. Edge exclusions tend to measure 2 to 8millimeters radially outward from the innermost useable diameter to theedge of the wafer.

Typically, methods are used to maximize the amount of available useablearea for chips on the semiconductor wafer. One such method attempts tomaximize the number of good chips obtainable from a wafer by changingthe center point of the wafer map. Referring to FIG. 1, a semiconductorwafer 10 is shown. A wafer map 20 is a layout of integrated circuitchips 12 on a wafer 18 which accounts for cuts between the chips aswell. Wafer map 20 is fixed in defining the locations of individualchips 12 relative to one another. Wafer modeling programs are given awafer map center point 16 and a given edge exclusion as input. Thedistance between point A and point B is the edge exclusion for wafer 18.An exclusion zone 14 is created at the outside of the wafer. A chip 12that passes 3 mm past a diameter 22 is considered unusable. The wafermodeling program moves the wafer map by adjusting center point 16 withinthe region defined by diameter 22 until the maximum number of useablechips is achieved for a given edge exclusion.

Although this method gives the yield for the number of chips with agiven edge exclusion, the number of usable chips per wafer may drop offsignificantly for slightly increased edge exclusions. For example, chips12a, 12b and 12c are shown with corners in exclusion zone 14. If theedge exclusion is larger these chips may be deemed unusable by the priorart wafer modeling technique. However, some of the chips that extendinto exclusion zone 14 may be usable since the yield probability forchips increases with decreasing wafer radius. This means that chipseliminated based on geometry alone may in fact be useable.

Therefore, a need exists for increasing the yield of semiconductorwafers based on the actual yield due to a given edge exclusion.

SUMMARY OF THE INVENTION

A method of fabricating semiconductor chips includes the steps ofoptimizing a number of chips that geometrically fit on a wafer andmaximizing chip yield for the wafer by considering chips located in anormally rejectable location and utilizing yield probability data forthe chip in the normally rejectable locations to weight the probabilityof an acceptable chip such that if the probability is above a thresholdvalue the chips are not rejected. This results in an increased chipyield for semiconductor wafers.

In particularly preferred methods of fabricating semiconductor chips thestep of optimizing a number of chips that geometrically fit on a waferincludes providing a predetermined wafer map for overlaying the wafer,the wafer map being referenced from a center point thereon andmaximizing a first quantity of chips that can fit on the wafer byvarying the center point of the wafer map on the wafer. The step ofmaximizing chip yield includes determining the quantity of chips thatcan fit on the wafer by varying an edge exclusion distance with a wafermap fixed at a maximized center point location, providing a yieldprobability curve for wafer map locations, multiplying the yieldprobability curve by the quantity of chips at each of the wafer maplocations to obtain a weighted yield probability curve for each wafermap center point location, comparing alternative the weightedprobability curves for different wafer map center point locations, andselecting the wafer map center point location to maximize the chip yieldfor the wafer. The steps of optimizing a number of chips thatgeometrically fit on a wafer and maximizing chip yield for the wafer maybe performed by a computer.

BRIEF DESCRIPTION OF DRAWINGS

This disclosure will present in detail the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a plan view of a wafer having a wafer map with chip locationsdisposed thereon;

FIG. 2 is a plot showing chips per wafer versus edge exclusion for atypical wafer;

FIG. 3 is a plot showing chips per wafer on a left vertical axis andyield probability on a right vertical axis, both versus edge exclusionon a horizontal axis; and

FIG. 4 is a plot of weighted yield probability versus edge exclusion.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present disclosure describes a method for maximizing the chip yieldfor a semiconductor wafer. By introducing yield probability data into awafer modeling program the number of usable chips can be increased for awafer. The present method typically improves the yield in situationswhere an edge exclusion for a wafer is relatively larger. The methodtakes yield data collected for a given type of chip and weights the chiplocation on the wafer in accordance with the yield data. Since largeedge exclusions equate to chips deemed unusable in the prior arttechnique, the weighting of yield probability saves some of these chipsbased on their location on the wafer. This results in a larger number ofchips for a given wafer.

Referring now in specific detail to the drawings in which like referencenumerals identify similar or identical elements throughout the severalviews, and initially to FIG. 2, the number of chips per wafer versusedge exclusion in millimeters is shown. The vertical axis of FIG. 2shows the number of integrated circuit chips that can be fabricated froma wafer. The wafer is an eight inch wafer, for example. The horizontalaxis of FIG. 2 represents the edge exclusion dimension for a given chipin millimeters. The range of the horizontal axis can be, for example,between 2 mm and 8 mm. This range is determined by wafer map centerpoint 16 (FIG. 1) which is limited in its displacement due to thegeometries of wafer map 20 and wafer 18. FIG. 2 is a plot of a curve 210of a wafer modeler in which center point 16 of wafer map 20 was variedfor a given edge exclusion until the maximum number of chips isdeternined. Generally, the variation shown in the maximum number ofchips for a given edge exclusion decreases as the edge exclusionincreases.

Of interest are corners 212 which are at the ends of horizontal linesegments of curve 210. A horizontal line in FIG. 2 denotes no decreasein the number of chips for a given edge exclusion. This means that asthe edge exclusion is increased the number of chips remains relativelyconstant over a given range of edge exclusion distance. This is typicalfor wafer modeling graphs which involve the circular geometry of thewafer and the rectangular shape of the chips. Several chips are deemedunusable simultaneously due to this geometrical mismatch. Referring toFIG. 1, as the edge exclusion distance (between point A and point B) isincreased several chip corners, for example 12a, 12b and 12c, movedeeper into exclusion zone 14 and are no longer deemed to be usable.

In order to demonstrate the method of the present disclosure two pointshave been designated in FIG. 2. Point 1, as indicated, shows that awafer that is eight inches in diameter has a chip yield of 146 chips ifan edge exclusion is 4.6 millimeters. Point 2, as indicated, shows thata wafer that is eight inches in diameter has a chip yield of 140 chipsif an edge exclusion is 6.85 millimeters. Both of these chip yieldsrepresent the maximum possible number of chips allowable due togeometry. The wafer modeler moves wafer map 20 by its center point 16 todetermine the maximum number of chips for wafer 10 given an edgeexclusion. See FIG. 1. FIG. 2 illustrates the prior art technique ofmaximizing the number of chips on a wafer. Based on FIG. 2, it appearsas though point 1 with a smaller edge exclusion would result in a higheryield, for example, 146 chips.

Referring to FIG. 3, a left vertical axis of FIG. 3 shows the number ofintegrated circuit chips that can be fabricated from a wafer. The waferis an eight inch wafer, for example. A horizontal axis of FIG. 3represents the edge exclusion for a given chip in millimeters. The rangeof the horizontal axis can be between 2 mm and 8 mm as in FIG. 2.

FIG. 3 illustrates the yield for a given edge exclusion when the centerpoint of the wafer map is held fixed.

Three curves are shown in FIG. 3. A first curve 310 shows the chip yieldper wafer over the range of edge exclusions with the center point fixedat the location determined by the wafer modeler for point 1 in FIG. 2. Asecond curve 312 shows the chip yield per wafer over the range of edgeexclusions with the center point fixed at the location determined by thewafer modeler for point 2 in FIG. 2.

In maintaining a fixed center point and moving from smaller edgeexclusions (2 mm) to larger edge exclusions (8 mm), it becomes apparentthat the number of chips per wafer drops off more rapidly for curve 310than curve 312 at an edge exclusion of approximately 4.6 mm. This dropoff is a result of more chip area falling into area in which chips arenormally rejected as the edge exclusions is increased. Although thesechips are deeper into exclusion zone 14 (FIG. 1) they may still beuseable. A method of identifying usable chips in the exclusion zone isoutlined in more detail hereinafter.

Yield probability for an individual chip increases as the location ofthe chip is closer to the center of the wafer. This is illustrated by acurve 314. Curve 314 has a right vertical axis which denotes yieldprobability as a percent value. Curve 314 uses the same horizontal axisfor edge exclusion as before. As illustrated by curve 314, yieldprobability increases for larger edge exclusions. Curve 314 is a typicalyield probability curve for manufacturing chips.

Despite the higher number of chips per wafer given initially for point 1in FIG. 2, the wafer map center point may have moved more chips closerto the edge of a wafer thereby decreasing the number of usable chips dueto their location on the wafer (increased distance from wafer center,therefore decreasing their yield probability). Curve 312 illustratesthat for larger edge exclusions a plateau 316 remains constant over theillustrated range of edge exclusions. This signifies a potentialadvantage to replacing the center point of the wafer map from thelocation corresponding to point 1 (146 chips available) to the locationcorresponding to point 2 (140 chips available) in FIG. 2 for wafers withlarger edge exclusions. This determination is based on the overall yieldof the chips including those in exclusion zone 14 (FIG. 1) and not justgeometrically fitting wafer map 20 on wafer 10 and eliminating thosechips that fall into the exclusion zone.

Referring now to FIGS. 1 and 4, a comparison may be made betweenlocations of wafer map 20 on wafer 10 which incorporates the yieldprobability into the placement of the wafer map center. A method forincorporating yield probability into the placement of the wafer mapincludes obtaining wafer map center locations on a wafer by determiningcorner points 212 as illustrated in FIG.2. This is completed by assuminga value for an edge exclusion and varying the center of the wafer map todetermine which location will allow the most chips to fit within thebounds of the edge exclusion based on geometry alone. This determinationcan be performed by an appropriately programmed computer.

Upon determining corner points 212, a corresponding center point 16 forthe wafer map is determined. Using the location of center points 16,curve 310 and 312 of FIG. 3 are generated for the center points 16corresponding to point 1 and point 2 of FIG. 2. The generation of curves310 and 312 can be performed by an appropriately programmed computer.Curves 310 and 312 are generated by fixing the center point 16 locationand varying the edge exclusion to determine the number of chips that canfit within the bounds of the edge exclusion as in FIG. 3. Curves 310 and312 (FIG. 3) are each multiplied by the yield probability curve 314 forthe overall chip manufacturing process. Yield probability data at eachedge exclusion dimension in FIG. 3 is multiplied by the correspondingvalue at the same edge exclusion value on the chips per wafer axis toobtain the plots shown in FIG. 4.

With further reference to FIG. 4, a curve 410 is generated as a resultof yield probability curve 314 and curve 310 multiplication. A curve 412is generated in a similar way but by multiplying curve 314 by curve 312.A comparison may now be made between two alternative placements of wafermap center point 16 which includes the overall yield of the chips. Thearea under curve 410 and curve 412 is taken in the edge exclusion rangebetween 2 mm and 8 mm, for example. The greater value of the area undereach curve gives the most favorable yield probability. The generation ofcurves 410 and 412 can be performed by an appropriately programmedcomputer, and the areas under curves 410 and 412 can be computed using anumerical integration program, for example. In FIG. 4, curve 412 gives asuperior location for the center point of the wafer map. As graphicallyillustrated a region 414 and a region 416 exceed the area of region 418.Therefore, the location that would have been rejected in the prior art,for example point 2 of FIG. 1, provides a greater overall yield ofusable chips since the location of the individual chips that would havebeen rejected may now be used based on the weight of the yieldprobability data which shows how successful a chip at a given locationfares during acceptance testing.

The best overall yield is provided for a given wafer using the weightingof the yield probability curve. Rather than determining the maximumamount of chips per wafer based on a particular edge exclusion alone,chip yield data is used to adjust for the weighting of the location ofthe wafer map. Yield increases can range for example, from 1-3% forwafer sizes of eight inches although higher yields are contemplated. Achip located at a position that was normally rejected due to itslocation in an exclusion zone of a wafer can now be considered for usebased on the yield probability associated with its position on thewafer. If the yield probability for the chip at this location is abovean assigned threshold value the chip can be accepted for use, henceincreasing the overall yield for a given wafer.

Having described embodiments of a method of maximizing the overall yieldof chips per semiconductor wafer (which are intended to be illustrativeand not limiting), it is noted that modifications and variations can bemade by persons skilled in the art in light of the above teachings. Itis therefore to be understood that changes may be made in the particularembodiments of the invention disclosed which are within the scope andspirit of the invention as delined by the appended claims. Having thusdescribed the invention with the details and particularity required bythe patent laws, what is claimed and desired protected by Letters Patentis set forth in the appended claims.

What is claimed is:
 1. A method of fabricating semiconductor chipscomprising the steps of:optimizing a number of chips that geometricallyfit on a wafer; and maximizing chip yield for the wafer by:consideringchips located in a normally rejectable location on the wafer; utilizingyield probability data for at least one of the chips in the normallyrejectable locations to weigh the probability of an acceptable chip suchthat if the probability is above a threshold value for the at least oneof the chips, the at least one of the chips is not rejected.
 2. Themethod of fabricating semiconductor chips as recited in claim 1 whereinthe step of optimizing a number of chips that geometrically fit on awafer includes providing a predetermined wafer map for overlaying thewafer, the wafer map being referenced from a center point thereon; andmaximizing a first quantity of chips that can fit on the wafer byvarying the
 3. The method of fabricating semiconductor chips as recitedin claim 1 wherein the step of maximizing chip yieldincludes:determining the quantity of chips that can fit on the wafer byvarying an edge exclusion distance with a wafer map fixed at a maximizedcenter point location; providing a yield probability curve for wafer maplocations; multiplying the yield probability curve by the quantity ofchips at each of the wafer map locations to obtain a weighted yieldprobability curve for each wafer map center point location; comparingweighted probability curves for different wafer map center pointlocations; and selecting the wafer map center point location to maximizethe chip yield for the wafer.
 4. The method of fabricating semiconductorchips as recited in claim 1 wherein the wafer is about eight inches indiameter.
 5. The method of fabricating semiconductor chips as recited inclaim 1 wherein the steps of optimizing a number of chips thatgeometrically fit on a wafer and maximizing chip yield for the wafer areperformed by a computer.
 6. A method of fabricating semiconductor chipscomprising the steps of:providing a predetermined wafer map foroverlaying a wafer, the wafer map being referenced from a center pointthereon; maximizing a first quantity of chips that can fit on the waferby varying the center point of the wafer map on the wafer; recording amaximized wafer map center point location; determining the quantity ofchips that can fit on the wafer by varying edge exclusion distances withthe wafer map fixed at the maximized center point location; providing ayield probability curve for wafer map locations; multiplying the yieldprobability curve by the quantity of chips at each of the wafer maplocations to obtain a weighted yield probability curve for each wafermap center point location; comparing weighted probability curves fordifferent wafer map center point locations; and selecting the wafer mapcenter point location to maximize the chip yield for the wafer.
 7. Themethod of fabricating semiconductor chips as recited in claim 6 whereinthe wafer is about eight inches in diameter.
 8. The method offabricating semiconductor chips as recited in claim 6 wherein edgeexclusion distances vary between 2 millimeters and 8 millimeters.
 9. Themethod of fabricating semiconductor chips as recited in claim 6 whereinthe steps of multiplying the yield probability curve by the quantity ofchips at each of the wafer map locations and comparing center pointlocations to maximize the chip yield for a wafer are performed by acomputer.
 10. A method of maximizing chip yield comprising the stepsof:determining a quantity of chips that can fit on a wafer by varying anedge exclusion distance with a wafer map fixed at a maximized centerpoint location; providing a yield probability curve for wafer maplocations; multiplying the yield probability curve by the quantity ofchips at each of the wafer map locations to obtain a weighted yieldprobability curve for each wafer map center point location; comparingweighted probability curves for different wafer map center pointlocations; and selecting the wafer map center point location to maximizethe chip yield for the wafer.
 11. The method as recited in claim 10,further comprising the step of maximizing the quantity of chips that canfit on the wafer by varying a center point of the wafer map on thewafer.
 12. The method as recited in claim 10, wherein edge exclusiondistances vary between 2 millimeters and 8 millimeters.